An Extrinsic Function-Level Evolvable Hardware Approach
Proceedings of the European Conference on Genetic Programming
Proceedings of the European Conference on Genetic Programming
A Divide-and-Conquer Approach to Evolvable Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Bridging The Genotype-Phenotype Mapping For Digital Fpgas
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
From Here To There: Future Robust Ehw Technologies For Large Digital Designs
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Evolvable Hardware Solutions For Extreme Temperature Electronics
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
On Evolution of Relatively Large Combinational Logic Circuits
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
A multi-chromosome approach to standard and embedded cartesian genetic programming
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Adaptive and Evolvable Hardware - A Multifaceted Analysis
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Toward self-adaptive embedded systems: multi-objective hardware evolution
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Generalized Disjunction Decomposition for Evolvable Hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
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Evolvable Hardware(EHW) has been proposed as a promising technology for adaptive systems in last few years. However, in practical applications, evolutionary algorithms(EAs) often need numerous generations to search a new solution. In general, a mistaken system is damaged if it cannot restore in time, so the inefficiency problem has become an obstacle of developing adaptive and evolvable hardware. This paper analyzes how those three factors as genotype, algorithm, and methodology affect the efficiency of the EAs, as well as to what extent of their influence respectively, then proposes parallel and recursive decomposition (PRD) as a new decomposition strategy to accelerate the adaptation process from methodology perspective. Finally, some adaptive combination logical circuits are implemented on Xilinx Virtex-II Pro (XC2VP20) FPGA. The results demonstrate that PRD has more improvement on adaptation speed than some previous strategies.