Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
Evolvable hardware chip for high precision printer image compression
AAAI '98/IAAI '98 Proceedings of the fifteenth national/tenth conference on Artificial intelligence/Innovative applications of artificial intelligence
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Proceedings of the European Conference on Genetic Programming
Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems
Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
A Divide-and-Conquer Approach to Evolvable Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
On Evolution of Relatively Large Combinational Logic Circuits
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Development Brings Scalability to Hardware Evolution
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Evolutionary Design of Digital Circuits: Where Are Current Limits?
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Using negative correlation to evolve fault-tolerant circuits
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Using genetic programming and high level synthesis to design optimized datapath
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
IEEE Transactions on Evolutionary Computation
Generalized Disjunction Decomposition for Evolvable Hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Hi-index | 0.00 |
In this paper, a stepwise dimension reduction (SDR) approach to evolutionary design of relatively large combinational logic circuits is proposed. The proposed method divides the whole circuit into several layers. As for a circuit with one output, the number of input combinations is expected to be reduced layer-by-layer. The current layer's outputs are the next layer's inputs. All layers are evolved separately one after another, and assembled to form a final solution. The experimental results of SDR on parities, multipliers and circuits taken from MCNC library are comparable with those of GDD. Especially, the 19-parity circuit can be evolved successfully.