Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
Hierarchical learning with procedural abstraction mechanisms
Hierarchical learning with procedural abstraction mechanisms
Genetic programming: an introduction: on the automatic evolution of computer programs and its applications
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Development and Evolution of Hardware Behaviors
Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
Evolvable Systems in Hardware Design: Taxonomy, Survey and Applications
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
Grammatical Evolution: Evolving Programs for an Arbitrary Language
EuroGP '98 Proceedings of the First European Workshop on Genetic Programming
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Evolutionary Multiobjective Design of Combinational Logic Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Genetic programming using genotype-phenotype mapping from linear genomes into linear phenotypes
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
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This paper presents a methodology to design optimized electronic digital systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-level synthesis tools to automatically improve design structural quality (area measure). A two-stage, multiobjective optimization algorithm is used to search for circuits with the desired functionality subjected additionally to chip area constraints. Experiment with a square-root approximation datapath design targeted to FPGA exemplifies the proposed methodology.