A Short Tutorial on Evolutionary Multiobjective Optimization
EMO '01 Proceedings of the First International Conference on Evolutionary Multi-Criterion Optimization
Evolutionary morphogenesis for multi-cellular systems
Genetic Programming and Evolvable Machines
Comparative study of serial and parallel heuristics used to design combinational logic circuits
Optimization Methods & Software
ICAISC '08 Proceedings of the 9th international conference on Artificial Intelligence and Soft Computing
Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits
EvoWorkshops '09 Proceedings of the EvoWorkshops 2009 on Applications of Evolutionary Computing: EvoCOMNET, EvoENVIRONMENT, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, EvoNUM, EvoSTOC, EvoTRANSLOG
Use of particle swarm optimization to design combinational logic circuits
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Using genetic programming and high level synthesis to design optimized datapath
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Design of gate array circuits using evolutionary algorithms
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
A fuzzy-genetic decision support system for project team formation
Applied Soft Computing
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In this paper, we propose an evolutionary multiobjective optimization approach to design combinational logic circuits. The idea is to use a population-based technique that considers outputs of a circuit as equality constraints that we aim to satisfy. A small sub-population is assigned to each objective. After one of these objectives is satisfied, its corresponding sub-population is merged with the rest of the individuals in what becomes a joint effort to minimize the total amount of mismatches produced (between the encoded circuit and the truth table). Once a feasible individual is found, all individuals cooperate to minimize its number of gates. The approach seems to reduce the amount of computer resources required to design combinational logic circuits, when compared to our previous research in this area.