Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits

Authors:
Adam Slowik;Jacek M. Zurada
Affiliations:
Department of Electronics and Computer Science, Koszalin University of Technology, Koszalin, Poland 75-453;Department of Electrical and Computer Engineering, University of Louisville, Louisville, USA KY 40292
Venue:
EvoWorkshops '09 Proceedings of the EvoWorkshops 2009 on Applications of Evolutionary Computing: EvoCOMNET, EvoENVIRONMENT, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, EvoNUM, EvoSTOC, EvoTRANSLOG
Year:
2009

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Abstract

In the paper a possibility of evolutionary number of gate optimization in PLA circuits implemented in VLSI technology is presented. Multi-layer chromosomes and specialized genetic operators cooperating to them are introduced to proposed evolutionary algorithm. Due to multi-layer chromosome structures whole gates are transferred in the logic array without disturb in their structures during crossover operation. Results obtained in optimization of gate number in selection boxes of DES cryptographic algorithm are compared to results obtained using SIS program with different optimization scripts such as: rugged, algebraic, and boolean. Proposed method allows to reduce the gates number in optimized circuit. Results obtained using described evolutionary method are better than using other methods.