Use of particle swarm optimization to design combinational logic circuits

Authors:
Carlos A. Coello Coello;Erika Hernández Luna;Arturo Hernández Aguirre
Affiliations:
CINVESTAV-IPN, Evolutionary Computation Group, Depto. Ing. Eléctrica, México, D.F., Mexico;CINVESTAV-IPN, Evolutionary Computation Group, Depto. Ing. Eléctrica, México, D.F., Mexico;CIMAT, Guanajuato, Guanajuato, Mexico
Venue:
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Year:
2003

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Abstract

This paper presents a proposal based on binary particle swarm optimization to design combinational logic circuits at the gate-level. The proposed algorithm is validated using several examples from the literature, and is compared against a genetic algorithm (with integer representation), and against human designers who used traditional circuit design aids (e.g., Karnaugh Maps). Results indicate that particle swarm optimization may be a viable alternative to design combinational circuits at the gate-level.