DAC '94 Proceedings of the 31st annual Design Automation Conference
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping
EURO-DAC '94 Proceedings of the conference on European design automation
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation
IEEE Transactions on Computers
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast OFDD-Based Minimization of Fixed Polarity Reed-Muller Expressions
IEEE Transactions on Computers
On the Expressive Power of OKFDDs
Formal Methods in System Design
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On a New Boolean Function with Applications
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pseudo-Kronecker Expressions for Symmetric Functions
IEEE Transactions on Computers
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Optimal low powerX OR gate decomposition
Proceedings of the 37th Annual Design Automation Conference
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Multi-output functional decomposition with exploitation of don't cares
Proceedings of the conference on Design, automation and test in Europe
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Information Content of the Ternary Decision Diagrams
Automation and Remote Control
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Structure Theorems for Closed Sets of Implicates/ Implicants in Temporal Logic
EPIA '99 Proceedings of the 9th Portuguese Conference on Artificial Intelligence: Progress in Artificial Intelligence
Efficient Decomposition Techniques for FPGAs
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Ant Colony System for the Design of Combinational Logic Circuits
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
Efficient Graph Coloring by Evolutionary Algorithms
Proceedings of the 6th International Conference on Computational Intelligence, Theory and Applications: Fuzzy Days
Automated deduction for many-valued logics
Handbook of automated reasoning
A cellular array designed from a Multiple-valued Decision Diagram and its fault tests
ATS '95 Proceedings of the 4th Asian Test Symposium
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An Implicit Algorithm for Support Minimization during Functional Decomposition
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Testability of 2-level AND/EXOR circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A New Method of Coding Minorants in Problems of Synthesis of Digital Devices from PLAs
Cybernetics and Systems Analysis
Planar Multiple-Valued Decision Diagrams
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
On Input Permutation Technique for Multiple-Valued Logic Synthesis
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Decomposition of Multiple-Valued Functions
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Fibonacci spectral transforms: calculation, algorithms and circuit realizations
Systems Analysis Modelling Simulation - Special issue: Digital signal processing and control
Design of combinational logic circuits through an evolutionary multiobjective optimization approach
Artificial Intelligence for Engineering Design, Analysis and Manufacturing
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient Realization of Parity Prediction Functions in FPGAs
Journal of Electronic Testing: Theory and Applications
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs
Journal of Electronic Testing: Theory and Applications
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Comparative study of serial and parallel heuristics used to design combinational logic circuits
Optimization Methods & Software
Microprocessor-based neural network controller of a stepper motor for a manipulator arm
NN'08 Proceedings of the 9th WSEAS International Conference on Neural Networks
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
Use of particle swarm optimization to design combinational logic circuits
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Computing support-minimal subfunctions during functional decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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