GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation
IEEE Transactions on Computers
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
C-testable bit parallel multipliers over GF(2m)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transition faults detection in bit parallel multipliers over GF(2m)
WSEAS Transactions on Circuits and Systems
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
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A new testable realization of Generalized Reed-Muller (GRM) expression with tree implementation of the EXOR-part is presented. This solves an open problem of designing an EXOR-tree based GRM network that admits a universal test set. For an n-variable function, the proposed design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR- and AND-type) and all single stuck-at faults. The EXOR-part is designed as a tree of depth ([log2s] + 1), where s is the number of product terms in the given GRM expression. This reduces circuit delay significantly compared to cascaded EXOR-part. Further, for several benchmark circuits, the test set is found to be much smaller than those of the earlier tree-based designs.