Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Fast Algorithms for Digital Signal Processing
Fast Algorithms for Digital Signal Processing
Error-Control Coding for Data Networks
Error-Control Coding for Data Networks
Transition Fault Simulation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Static compaction for two-pattern test sets
ATS '95 Proceedings of the 4th Asian Test Symposium
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
IEEE Design & Test
A Theory of Galois Switching Functions
IEEE Transactions on Computers
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this article, a C-testable design for detecting transition faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m) is discussed. For 100 percent transition fault coverage, the proposed technique requires only 10 vectors, irrespective of multiplier size, at the cost of 6 percent extra hardware. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a Built-in Self-Test (BIST) circuit may be used for generating test patterns internally. This will obviate the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using Synopsys® tools with 0.18µ CMOS technology library from UMC.