DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Compact test sets for digital logic circuits
Compact test sets for digital logic circuits
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
Journal of Electronic Testing: Theory and Applications
On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
Transition faults detection in bit parallel multipliers over GF(2m)
WSEAS Transactions on Circuits and Systems
Chiba Scan Delay Fault Testing with Short Test Application Time
Journal of Electronic Testing: Theory and Applications
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We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Experimental results are presented to evaluate the effectiveness of the compaction procedure.