A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits

Path delay fault testing using test points

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Static compaction for two-pattern test sets

ATS '95 Proceedings of the 4th Asian Test Symposium

20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Dynamic Test Compaction for Bridging Faults

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Path delay test compaction with process variation tolerance

Proceedings of the 42nd annual Design Automation Conference

A dynamic test compaction procedure for high-quality path delay testing

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

Journal of Electronic Testing: Theory and Applications

Switching activity as a test compaction heuristic for transition faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Function-based compact test pattern generation for path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths

Proceedings of the Conference on Design, Automation and Test in Europe