Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Proceedings of the conference on Design, automation and test in Europe
A Postprocessing Procedure of Test Enrichment for Path Delay Faults
ATS '04 Proceedings of the 13th Asian Test Symposium
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
A Critical Path Selection Method for Delay Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set for paths selected by a path selection criterion, the generated test set would detect not only faults on the selected paths but also faults on many unselected paths. Hence both high test quality by detecting untargeted faults and test cost reduction by reducing test patterns can be achieved. Experimental results show that the proposed procedure could generate a compact test set that detect many untargeted path delay faults certainly, compared with the static test compaction method previously proposed in [15].