Test set compaction algorithms for combinational circuits

Design of system-on-a-chip test access architectures under place-and-route and power constraints

Proceedings of the 37th Annual Design Automation Conference

Analysis and minimization of test time in a combined BIST and external test approach

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Proceedings of the conference on Design, automation and test in Europe

Synthesis of single-output space compactors with application to scan-based IP cores

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Optimal test access architectures for system-on-a-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Test volume and application time reduction through scan chain concealment

Proceedings of the 38th annual Design Automation Conference

Combining low-power scan testing and test data compression for system-on-a-chip

Proceedings of the 38th annual Design Automation Conference

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

Proceedings of the 39th annual Design Automation Conference

On Using Twisted-Ring Counters for Test Set Embedding in BIST

Journal of Electronic Testing: Theory and Applications

Reusing Scan Chains for Test Pattern Decompression

Journal of Electronic Testing: Theory and Applications

Test Resource Partitioning for SOCs

IEEE Design & Test

Compact two-pattern test set generation for combinational and full scan circuits

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Test application time and volume compression through seed overlapping

Proceedings of the 40th annual Design Automation Conference

Tailoring ATPG for Embedded Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference

On Static Test Compaction and Test Pattern Ordering for Scan Designs

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes

IEEE Transactions on Computers

Test vector decomposition-based static compaction algorithms for combinational circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

On test data volume reduction for multiple scan chain designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Test data compression using dictionaries with selective entries and fixed-length indices

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs

IEEE Transactions on Computers

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

Journal of Electronic Testing: Theory and Applications

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

Journal of Electronic Testing: Theory and Applications

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Combining dictionary coding and LFSR reseeding for test data compression

Proceedings of the 41st annual Design Automation Conference

On Compacting Test Response Data Containing Unknown Values

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Test data compression technique using selective don't-care identification

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

A New Approach to Test Generation and Test Compaction for Scan Circuits

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests

IEEE Transactions on Computers

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Hybrid BIST Based on Repeating Sequences and Cluster Analysis

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Evaluation of Error-Resilience for Reliable Compression of Test Data

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Using MUXs Network to Hide Bunches of Scan Chains

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Dynamic Test Compaction for Bridging Faults

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression

Journal of Electronic Testing: Theory and Applications

Enhancing error resilience for reliable compression of VLSI test data

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Path delay test compaction with process variation tolerance

Proceedings of the 42nd annual Design Automation Conference

Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Frugal linear network-based test decompression for drastic test cost reductions

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

A dynamic test compaction procedure for high-quality path delay testing

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Concurrent core test for SOC using shared test set and scan chain disable

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Test resource partitioning based on efficient response compaction for test time and tester channels reduction

Journal of Computer Science and Technology

On test data compression using selective don't-care identification

Journal of Computer Science and Technology

Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs

IEEE Transactions on Computers

On test generation by input cube avoidance

Proceedings of the conference on Design, automation and test in Europe

Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs

Proceedings of the conference on Design, automation and test in Europe

Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A selective pattern-compression scheme for power and test-data reduction

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

GECOM: test data compression combined with all unknown response masking

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

On reducing both shift and capture power for scan-based testing

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

A novel test-data compression technique using application-aware bitmask and dictionary selection methods

Proceedings of the 18th ACM Great Lakes symposium on VLSI

Leakage current optimization techniques during test based on don't care bits assignment

Journal of Computer Science and Technology

iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing

Proceedings of the conference on Design, automation and test in Europe

On capture power-aware test data compression for scan-based testing

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Dynamic test compaction for a random test generation procedure with input cube avoidance

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

Journal of Electronic Testing: Theory and Applications

Definition and application of approximate necessary assignments

Proceedings of the 19th ACM Great Lakes symposium on VLSI

State persistence: a property for guiding test generation

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Improving linear test data compression

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Forward-looking reverse order fault simulation for n-detection test sets

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Genetic algorithm for test pattern generator design

Applied Intelligence

Multiple scan trees synthesis for test time/data and routing length reduction under output constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On clustering of undetectable single stuck-at faults and test quality in full-scan circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme

Proceedings of the Conference on Design, Automation and Test in Europe

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

Test data compression using efficient bitmask and dictionary selection methods

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping

Journal of Electronic Testing: Theory and Applications

MICRO: a new hybrid test data compression/ decompression scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Random test generation with input cube avoidance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Test Data Compression Using Selective Sparse Storage

Journal of Electronic Testing: Theory and Applications

Test data compression using interval broadcast scan for embedded cores

Microelectronics Journal

A new scheme of test data compression based on equal-run-length coding (ERLC)

Integration, the VLSI Journal

Deterministic test vector compression / decompression using an embedded processor

EDCC'05 Proceedings of the 5th European conference on Dependable Computing

COMPAS – compressed test pattern sequencer for scan based circuits

EDCC'05 Proceedings of the 5th European conference on Dependable Computing

Test data compression using four-coded and sparse storage for testing embedded core

ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II

An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

Journal of Signal Processing Systems

Virtual scan chains reordering using a RAM-based module for high test compression

Microelectronics Journal

Techniques for SAT-based constrained test pattern generation

Microprocessors & Microsystems

Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Journal of Electronic Testing: Theory and Applications

Improved SAT-based ATPG: more constraints, better compaction

Proceedings of the International Conference on Computer-Aided Design