Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Minimal Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test Pattern Generation with Restrictors
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Reusing Scan Chains for Test Pattern Decompression
ETW '01 Proceedings of the IEEE European Test Workshop (ETW'01)
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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An automatic test pattern generation (ATPG)method is presented for a scan-based test architecture which minimizesATE storage requirements and reduces the bandwidth betweenthe automatic test equipment (ATE) and the chip under test.To generate tailored deterministic test patterns, a standard ATPGtool performing dynamic compaction and allowing constraints oncircuit inputs is used. The combination of an appropriate test architectureand the tailored test patterns reduces the test data volumeup to two orders of magnitude compared with standard compactedtest sets.