Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Scan chain organization for embedded diagnosis
Proceedings of the conference on Design, automation and test in Europe
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
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The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.