STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test Data Compression Using Don't-Care Identification and Statistical Encoding
ATS '02 Proceedings of the 11th Asian Test Symposium
Reusing Scan Chains for Test Pattern Decompression
ETW '01 Proceedings of the IEEE European Test Workshop (ETW'01)
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Random Access Scan: A solution to test power, test data volume and test time
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Localized random access scan: towards low area and routing overhead
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the random access scan (RAS) scheme offers a solution to alleviate the above problems (Baik et al., 2004). In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, test response abundant, constrained static compaction, and bit propagation before test vector dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.