Random Access Scan: A solution to test power, test data volume and test time

Authors:
Dong Hyun Baik;Kewal K. Saluja;Seiji Kajihara
Affiliations:
-;-;-
Venue:
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Year:
2004

Citing 0
Cited 5

A cocktail approach on random access scan toward low power and high efficiency test

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An overlapping scan architecture for reducing both test time and test power by pipelining fault detection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Localized random access scan: towards low area and routing overhead

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Single cycle access structure for logic test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Adherence to serial scan is preventing the researchersfrom investigating alternative design for test techniquesthat may offer larger test benefit at the cost of somewhat higher overhead.In this paper, we investigate theuse of random access scan for simultaneous reduction oftest power, test data volume and test application time.We provide an asymmetric traveling salesman formulationof these problems to minimize random access scansand the test data.Application of our method resultsinto nearly 3x speedup in test application time, 60% reductionin test data volume and over 99% reduction inpower consumption for benchmark circuits.