Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Automatic incorporation of on-chip testability circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Random Access Scan: A solution to test power, test data volume and test time
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IEICE - Transactions on Information and Systems
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.