The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Designing Circuits with Partial Scan
IEEE Design & Test
Synthesizing Circuits with Implicit Testability Constraints
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Optimal Sequencing of Scan Registers
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Synthesis Approach to Design for Testability
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Scan insertion criteria for low design impact
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Synthesis-for-scan and scan chain ordering
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power-Driven Routing-Constrained Scan Chain Design
Journal of Electronic Testing: Theory and Applications
Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Routing-aware scan chain ordering
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Routing-aware scan chain ordering
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Localized random access scan: towards low area and routing overhead
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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A new practical layout-based approach forordering flip-flop scan chains is presented. Thisapproach can reduce the stitching wire length byan order of magnitude, and dramaticallyimprove circuit routablility.