Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage

Authors:
Puneet Gupta;Andrew B. Kahng;Ion Mandoiu;Puneet Sharma
Affiliations:
University of California at San Diego;University of California at San Diego;University of Connecticut, Storrs;University of California at San Diego
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

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Abstract

Path delay fault testing becomes increasingly important due tohigher clock rates and higher process variability caused by shrinkinggeometries. Achieving high-coverage path delay fault testingrequires the application of scan justified test vector pairs, coupledwith careful ordering of the scan flip-flops and/or insertion ofdummy flip-flops in the scan chain. Previous works on scan synthesisfor path delay fault testing using scan shifting have focusedexclusively on maximizing fault coverage and/or minimizing thenumber of dummy flip-flops, but have disregarded the scan wirelengthoverhead. In this paper we consider both dummy flip-flopand wirelength costs, and focus on post-layout formulations thatcapture the achievable tradeoffs between these costs and delay faultcoverage in scan chain synthesis.