A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
DAC '93 Proceedings of the 30th international Design Automation Conference
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
An optimal algorithm for cycle breaking in directed graphs
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
An exact algorithm for selecting partial scan flip-flops
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Design of testable sequential circuits by repositioning flip-flops
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Designing Circuits with Partial Scan
IEEE Design & Test
Partial Scan Testing on the Register-Transfer Level
Journal of Electronic Testing: Theory and Applications
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Routing-aware scan chain ordering
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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In an era of sub-micron technology, routing is becoming a dominant factor in area, timing, and power consumption.In this paper, we study the problem of selection and chaining of scan flip-flops with the objective of achieving minimum routing area overhead. Most of previous work on partial scan has put emphasis on selecting as few scan flip-flops as possible to break all cyclesin S-graph. However, the flip-flops that break more cycles areoften the ones that have more fanins and fanouts. The area adjacent to thesenodes is often crowded in layout. Such selections will cause layout congestion and increase the number of tracks to chain the scan flip-flops.To take layout information into consideration, we propose a matching-based algorithm to solve the problem. First, an initial placement will be performed before scan flip-flops are selected. Then, iteratively, a matching-based algorithm taking the current layout into account is proposedto select and chain the scan flip-flops. Experimental results show that, on the average, our algorithm can reduce 8.1% area overhead as compared with the previously proposed methods that do not utilize the layout information in flip-flop selection.