Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
Layout Driven Selection and Chaining of Partial Scan Flip-Flops
Journal of Electronic Testing: Theory and Applications
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Scanning datapaths: a fast and effective partial scan selection technique
Proceedings of the conference on Design, automation and test in Europe
Partial Scan Testing on the Register-Transfer Level
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
Cost-Driven Ranking of Memory Elements for Partial Intrusion
IEEE Design & Test
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test sequence compaction by reduced scan shift and retiming
ATS '95 Proceedings of the 4th Asian Test Symposium
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On the selection of a partial scan path with respect to target faults
EURO-DAC '91 Proceedings of the conference on European design automation
Optimization of Parallel-Series Self-Testing for Discrete Devices
Automation and Remote Control
Using a software testing technique to identify registers for partial scan implementation
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A hybrid fault simulator for synchronous sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
Built-in test strategy for next generation military avionic hardware
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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In this scan design methodology, only selected faults are targeted for detection. These faults are those not detected by the designer's functional vectors. The test generator decides exactly which flip-flops should be scanned using one of two methods. In the first method, all possible tests are generated for each target fault, and the set of tests requiring the fewest flip-flops is selected. In the second method, only one test is generated for each fault, and the use of flip-flops is avoided as much as possible during test generation. Examples of actual VLSI circuits show a savings of at least a 40% in full-scan overhead.