Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On the OBDD-Representation of General Boolean Functions
IEEE Transactions on Computers
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Designing Circuits with Partial Scan
IEEE Design & Test
PROOFS: a super fast fault simulator for sequential circuits
EURO-DAC '90 Proceedings of the conference on European design automation
On Redundancy and Fault Detection in Sequential Circuits
IEEE Transactions on Computers
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Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information available about the initial state of the circuit. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known that fault simulation based upon this logic only determines a lower bound for the fault coverage achieved by a test sequence. Therefore, we developed a hybrid fault simulator H-FS combining the advantages of a fault simulator using the three-valued logic and of an exact symbolic fault simulator bused upon binary decision diagrams. H-FS is able to handle even the largest benchmark circuits and thereby determines fault coverages much more accurately than previous algorithms using the three-valued logic.