Partial Scan Testing on the Register-Transfer Level

Authors:
Bruce S. Greene;Samiha Mourad
Affiliations:
Synopsys Inc., 700 E. Middlefield Way, Mountain View, CA 94043. bruceg@synopsis.com;William and Janice Terry Professor, Electrical Engineering Department, Santa Clara University, 500 El Camino Real, Santaclara, CA 95053. smourad@scu.edu
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2002

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Abstract

This paper presents a methodology to insert scan paths in a design that is specified on the Register Transfer Level (RT-Level). The results indicate that selecting registers on this level guarantees a reduction in DFT design time and improvement of fault coverage, without incurring high hardware overhead.