An exact algorithm for selecting partial scan flip-flops

Selecting partial scan flip-flops for circuit partitioning

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications

DAC '94 Proceedings of the 31st annual Design Automation Conference

Resynthesis and retiming for optimum partial scan

DAC '94 Proceedings of the 31st annual Design Automation Conference

Partial scan with pre-selected scan signals

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Test register insertion with minimum hardware cost

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Cost-free scan: a low-overhead scan path design methodology

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Oscillation control in logic simulation using dynamic dominance graphs

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Partial scan design based on circuit state information

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Full scan fault coverage with partial scan

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Incremental Testability Analysis for Partial Scan Selection and Design Transformations

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop

Automated phase assignment for the synthesis of low power domino circuits

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Partial Scan with Preselected Scan Signals

IEEE Transactions on Computers

Partial BIST insertion to eliminate data correlation

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability

Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification

Deterministic BIST with Partial Scan

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Behavioral-Level DFT via Formal Operator Testability Measures

Journal of Electronic Testing: Theory and Applications

Partial Scan Testing on the Register-Transfer Level

Journal of Electronic Testing: Theory and Applications

A layout-based approach for ordering scan chain flip-flops

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Testable design of non-scan sequential circuits using extra logic

ATS '95 Proceedings of the 4th Asian Test Symposium

Software transformations for sequential test generation

ATS '95 Proceedings of the 4th Asian Test Symposium

Exploiting temporal independence in distributed preemptive circuit simulation

EDTC '97 Proceedings of the 1997 European conference on Design and Test

Partial scan design for technology mapped circuits

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Dynamic test Sequence compaction for Sequential Circuits

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Retiming with logic duplication transformation: theory and an application to partial scan

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Sequential Circuits with combinational Test Generation Complexity

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Deriving Signal Constraints to Accelerate Sequential Test Generation

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Partial Scan Using Multi-Hop State Reachability Analysis

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

An Integrated Approach to Behavioral-Level Design-For-Testability Using Value-Range and Variable Testability Techniques

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Partial Scan Design Based on Circuit State Information and Functional Analysis

IEEE Transactions on Computers

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency

Journal of Electronic Testing: Theory and Applications

Fast Computation of Data Correlation Using BDDs

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Hybrid Approach to Faster Functional Verification with Full Visibility

IEEE Design & Test

A New Design-for-Testability Method Based on Thru-Testability

Journal of Electronic Testing: Theory and Applications

Eliminating the Timing Penalty of Scan

Journal of Electronic Testing: Theory and Applications