The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan flip-flop selection by use of empirical testability
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
Proceedings of the IEEE International Test Conference
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost-free scan: a low-overhead scan path design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational automatic test pattern generation for acyclic sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test function embedding algorithms with application to interconnected finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A partition and resynthesis approach to testable design of large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Partial scan and non-scan techniques allow test generation of high fault coverage for sequential circuits with less area overhead and less performance degradation than full scan technique. In most of these techniques, extra logic (e.g. a multiplexer introduced by partial scan) is added to permit a data transfer from a flip-flop (or input) to another flip-flop (or output). Such additional logic function is called thru function in this paper, which plays an essential role in enhancing the testability of a circuit. In this paper, we introduce a design-for-testability (DFT) technique which modifies a given sequential circuit to a thru-testable sequential circuit with acyclic test generation complexity by adding new thru functions based on the information of thru functions that may exist in the original design and the dependency among these thru functions. Thus, thru functions of a given sequential circuit should first be extracted from its high-level description. If there is a thru function that transfers data from a flip-flop to another flip-flop, the latter is exempted from being considered in DFT insertion. This reduces the additional logic to be added. Using ITC'99 benchmark circuits, we show that the proposed DFT method takes up less area overhead compared to the previous scan methods in testing the difficult-to-test circuits like b07, b08 and b15. Besides, the test application time is shorter than that of previous scan methods while the test data volume is less too in difficult-to-test circuits.