Overall consideration of scan design and test generation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
An algorithm to reduce test application time in full scan designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Serial-Scan Test-Vector-Compression Methodology
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Reduced scan shift: a new testing method for sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
A New Design-for-Testability Method Based on Thru-Testability
Journal of Electronic Testing: Theory and Applications
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a design-for-testability technique for synchronous sequential circuits called autoscan. Autoscan uses scan chains similar to conventional scan. However, it gives up the external scan inputs and outputs in order to eliminate the test data volume associated with them. Scan operations under autoscan improve the circuit testability by allowing the circuit state to be modified through shifting. Due to the removal of the scan inputs and outputs, synthesis of scan chains under autoscan does not have to satisfy all the constraints imposed on conventional scan chains. We describe a synthesis procedure for autoscan chains, and demonstrate that autoscan allows us to detect almost all the faults that are detectable using conventional scan. We use random sequences in order to show that sequential test generation is not necessary under autoscan. We also describe a test generation procedure, and discuss the effect of autoscan on fault diagnosis.