Logic testing and design for testability
Logic testing and design for testability
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sequential circuit testability enhancement using a nonscan approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
ATS '99 Proceedings of the 8th Asian Test Symposium
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency
ATS '98 Proceedings of the 7th Asian Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
On Minimally Testable Logic Networks
IEEE Transactions on Computers
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
Good Controllability and Observability Do Not Guarantee Good Testability
IEEE Transactions on Computers
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonscan design-for-testability techniques using RT-level design information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.01 |
A non-scan design for testability y method is presented for synchronous sequential circuits. A testability measure called conflict based on conflict analysisin the process of synchronous sequential circuit testgeneration is introduced. Reconvergent fan outs withnonuniform in version parity is still one of the maincauses of redundancy and backtracking in the processof sequential circuit test generation. A new conceptcalled sequential depth for testability is introduced tocalculate the conflict-analysis-based testability measure Potential conflicts between fault effect activation and fault effect propagation are also checked because they are closely related. The testability measure implies the number of potential conflicts to occur or the number of clock cycles required to detecta fault. The non-scan design for testability methodbased on the conflict measure can reduce many potential back tracks make many hard-to-detect faultseasy-to-detect and many redundant faults testabletherefore, can enhance fault coverage of the circuitgreatly. It is believed that non-scan design for testability using the conflict measure can improve the actualtestability of a circuit. Extensive experimental resultsare presented to demonstrate the effectiveness of themethod.