Constructive Multi-Phase Test Point Insertion for Scan-Based BIST

STARBIST: scan autocorrelated random pattern generation

DAC '97 Proceedings of the 34th annual Design Automation Conference

A hybrid algorithm for test point selection for scan-based BIST

DAC '97 Proceedings of the 34th annual Design Automation Conference

Test Data Decompression for Multiple Scan Designs with Boundary Scan

IEEE Transactions on Computers

Improving the test quality for scan-based BIST using a general test application scheme

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Distributed Generation of Weighted Random Patterns

IEEE Transactions on Computers

Circuit partitioning for efficient logic BIST synthesis

Proceedings of the conference on Design, automation and test in Europe

A testability metric for path delay faults and its application

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Application of Deterministic Logic BIST on Industrial Circuits

Journal of Electronic Testing: Theory and Applications

A novel combinational testability analysis by considering signal correlation

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Modular logic built-in self-test for IP cores

ITC '98 Proceedings of the 1998 IEEE International Test Conference

BETSY: synthesizing circuits for a specified BIST environment

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A Ring Architecture Strategy for BIST Test Pattern Generation

Journal of Electronic Testing: Theory and Applications

A scan BIST generation method using a markov source and partial bit-fixing

Proceedings of the 40th annual Design Automation Conference

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Application of Deterministic Logic BIST on Industrial Circuits

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Point Insertion for Compact Test Sets

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Scan Encoded Test Pattern Generation for BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Logic BIST for Large Industrial Designs: Real Issues and Case Studies

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Low Overhead Test Point Insertion For Scan-Based BIST

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution

IEEE Transactions on Computers

Impact of Test Point Insertion on Silicon Area and Timing during Layout

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Logic BIST Using Constrained Scan Cells

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

A BIST TPG for low power dissipation and high fault coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

Journal of Electronic Testing: Theory and Applications