DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
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This paper presents a logic synthesis tool calledBETSY (BIST Environment Testable SYnthesis) forsynthesizing circuits that achieve complete (100%) faultcoverage in a user specified BIST environment. Insteadof optimizing the circuit for a generic pseudo-random testpattern generator (by maximizing its random patterntestability), the circuit is optimized for a specific testpattern generator, e.g., an LFSR with a specificcharacteristic polynomial and initial seed. This solvesthe problem of having to estimate fault detectionprobabilities during synthesis and guarantees that theresulting circuit achieves 100% fault coverage. BETSYconsiders the exact set of patterns that will be applied tothe circuit during BIST and applies varioustransformations to generate an implementation that is fullytested by those patterns. When needed, BETSY insertstest points early in the synthesis process in an optimalway and accounts for them in satisfying timing constraintsand other synthesis criteria. Experimental results areshown which demonstrate the benefits of optimizing acircuit for a particular test pattern generator.