A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BETSY: synthesizing circuits for a specified BIST environment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modeling Fault Coverage of Random Test Patterns
Journal of Electronic Testing: Theory and Applications
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Test Point Insertion Algorithm for Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A New Multiple Weight Set Calculation Algorithm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low Overhead Test Point Insertion For Scan-Based BIST
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
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This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than using probabilistic techniques for test point placement, a path tracing procedure is used to place both control and observation points. Rather than adding extra scan elements to drive the control points, a few of the existing primary inputs to the circuit are ANDed together to form signals that drive the control points. By selecting which patterns the control point is activated for, the effectiveness of each control point is maximized. A comparison is made with the best previously published results for other test point insertion methods, and it is shown that the proposed method requires fewer test points and less overhead to achieve the same or better fault coverage.