Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Testability analysis and multi-frequency ATPG for analog circuits and systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Testability Features of the AMD-K6 Microprocessor
IEEE Design & Test
Linear Error Modeling of Analog and Mixed-Signal Devices
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Analog Fault Diagnosis for Unpowered Circuit Boards
Proceedings of the IEEE International Test Conference
TMEAS, a testability measurement program
DAC '79 Proceedings of the 16th Design Automation Conference
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test Points Selection Process and Diagnosability Analysis of Analog Integrated Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Hierarchical ATPG for Analog Circuits and Systems
IEEE Design & Test
LFSR-based BIST for analog circuits using slope detection
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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This paper presents an algorithm based on testability measurement for test point nsertion of mixed-signal circuits. Two transfer function models compatible with analog models are proposed: one is for digital devices and the other is for A/D interface components. An industry power supply circuit and a common A/D converter circuit are used to validate our approaches.