Design based analog testing by Characteristic Observation Inference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic test signal design for analog ICs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Testability analysis and multi-frequency ATPG for analog circuits and systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Analog Testing with Time Response Parameters
IEEE Design & Test
DC Built-In Self-Test for Linear Analog Circuits
IEEE Design & Test
Real-Time Current Testing for A/D Converters
IEEE Design & Test
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis
Proceedings of the IEEE International Test Conference
Stimulus generation for built-in self-test of charge-pump phase-locked loops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Oscillation-test strategy for analog and mixed-signal integrated circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Hierarchical Test Generation for Analog Circuits Using Incremental Test Development
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Test Point Insertion Algorithm for Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Effective Oscillation-Based Test for application to a DTMF Filter Bank
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Test Generation Algorithm for Linear Systems Based on Genetic Algorithm
Journal of Electronic Testing: Theory and Applications
Automatic linearity and frequency response tests with built-in pattern generator and analyzer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a hierarchical modeling technique which, when combined with a test pattern generation algorithm, forms a hierarchical automatic test pattern generation procedure for analog circuits and systems. This hierarchical procedure is demonstrated to be efficient in terms of both memory and computational speed, especially in processing large circuits. Several examples illustrate the hierarchical modeling technique. The test generation algorithm has been validated in several case studies, one of which is described in details. A prototype software tool is available for university and industry use, with possible enhancements to increase the tool applicability in specific design and test environments.