IEEE Transactions on Computers
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Multiple fault analog circuit testing by sensitivity analysis
Journal of Electronic Testing: Theory and Applications - Joint special issue on analog and mixed-signal testing
Fault-based automatic test generator for linear analog circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient DC fault simulation of nonlinear analog circuits
Proceedings of the conference on Design, automation and test in Europe
Hierarchical ATPG for Analog Circuits and Systems
IEEE Design & Test
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Analog and Mixed-Signal Benchmark Circuits - First Release
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An On-Chip Spectrum Analyzer for Analog Built-In Testing
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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DC testing of analog circuits is inexpensive compared to AC testing and provides high coverage of many fault classes including some that are not detected by AC tests. It is also particularly effective in detecting catastrophic failures such as line opens and shorts. In this article, we present an efficient low-cost built-in self-test (BIST) methodology for linear analog circuits that is targeted towards faults that can be detected with DC tests. The methodology is based on the use of checksum encodings of matrix representations of the DC transfer function of the circuit under test (CUT). A small amount of circuitry called the checking circuitry is appended to the CUT for the purpose of on-chip fault detection. In test mode, DC stimulus is applied to the CUT via low-cost on-chip BIST circuitry. The presence of a non-zero signal at the output of the checking circuit indicates the presence of a fault.