IEEE Transactions on Computers
The algebraic eigenvalue problem
The algebraic eigenvalue problem
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
IEEE Transactions on Computers
Efficient Calculation of the Effects of Roundoff Errors
ACM Transactions on Mathematical Software (TOMS)
Pracniques: further remarks on reducing truncation errors
Communications of the ACM
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Processor arrays for problems in computational physics (parallel)
Processor arrays for problems in computational physics (parallel)
Probabilistic Evaluation of Online Checks in Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations
IEEE Transactions on Computers
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
IEEE Transactions on Computers
Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems
IEEE Transactions on Computers
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization
IEEE Transactions on Computers
Generalized Algorithm-Based Fault Tolerance: Error Correction via Kalman Estimation
IEEE Transactions on Computers
An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship
IEEE Transactions on Computers
DC Built-In Self-Test for Linear Analog Circuits
IEEE Design & Test
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
IEEE Transactions on Computers
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems
IEEE Transactions on Computers
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Low-cost DC built-in self-test of linear analog circuits using checksums
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
On-Line Fault Detection In DSP Circuits Using Extrapolated Checksums with Minimal Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Failure-Detecting Arithmetic Convolutional Codes and an Iterative Correcting Strategy
IEEE Transactions on Computers
Integration, the VLSI Journal
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Wavelet codes: detection and correction using Kalman estimation
IEEE Transactions on Signal Processing
Optimal real number codes for fault tolerant matrix operations
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Nonconcurrent error correction in the presence of roundoff noise
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constructing numerically stable real number codes using evolutionary computation
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Numerically stable real number codes based on random matrices
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part I
A class of fault-tolerant systolic arrays for matrix multiplication
Mathematical and Computer Modelling: An International Journal
| Hi-index | 15.01 |
A generalization of existing real numer codes is proposed. It is proven that linearity is a necessary and sufficient condition for codes used for fault-tolerant matrix operations such as matrix addition, multiplication, transposition, and LU decomposition. It is also proven that for every linear code defined over a finite field, there exists a corresponding linear real-number code with similar error detecting capabilities. Encoding schemes are given for some of the example codes which fall under the general set of real-number codes. With the help of experiments, a rule is derived for the selection of a particular code for a given application. The performance overhead of fault tolerance schemes using the generalized encoding schemes is shown to be very low, and this is substantiated through simulation experiments.