Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Time redundant fault-location in bit-sliced ALU's
IEEE Transactions on Computers
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
A Linear Algebraic Model of Algorithm-Based Fault Tolerance
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Berger Check Prediction for Array Multipliers and Array Dividers
IEEE Transactions on Computers
Error Analysis for the Support of Robust Voltage Scaling
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Specification and synthesis of hardware checkpointing and rollback mechanisms
Proceedings of the 49th Annual Design Automation Conference
| Hi-index | 14.98 |
Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers.