Design of Self-Testing Checkers for Borden Codes
IEEE Transactions on Computers
Concurrent error detection in VLSI interconnection networks
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Design of self-checking digital networks using coding techniques
Design of self-checking digital networks using coding techniques
A New Design Method for m-Out-of-n TSC Checkers
IEEE Transactions on Computers
Design of Fail-Safe Sequential Machines Using Separable Codes
IEEE Transactions on Computers
Design of a Self-Checking Microprogram Control
IEEE Transactions on Computers
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ± 1) Codes
IEEE Transactions on Computers
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes
IEEE Transactions on Computers
Partially Self-Checking Circuits and Their Use in Performing Logical Operations
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
Note on Self-Checking Checkers
IEEE Transactions on Computers
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Intermediacy Prediction for High Speed Berger Code Checkers
Journal of Electronic Testing: Theory and Applications
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
IEEE Transactions on Computers
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme
IEEE Transactions on Computers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the 47th Design Automation Conference
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
| Hi-index | 15.00 |
The Berger codes are optimal separable codes that detect all undirectional errors. In this correspondence a new procedure of designing self-testing checkers (STC's) for codes with I information bits, where I = {2K-2, 2K-l} and I = 3, is proposed. I = 3. The new checker is basically composed of u = ?(I + 1)/2? STC's for m-out-of-n codes with n = I + 1 and m = 2p + 1, O = p = u