Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
IEEE Transactions on Computers
Modular implementation of efficient self-checking checkers for the Berger code
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Fast and area-time efficient Berger code checkers
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Scaling Deeper to Submicron: On-Line Testing to the Rescue
ITC '98 Proceedings of the 1998 IEEE International Test Conference
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
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We present an intermediacy prediction method that can be used to designhigh speed checkers for Berger codes, as well as for any other unordered code. In the proposed method, the received information and check bits are processed simultaneously toward an intermediate result. A two-rail code checker is then used to compare the two versions of such an intermediate result. Recall that, in conventional checkers for unordered codes, the received check bits remain idle until the received information bits are converted to the re-generated check bits. Therefore, our proposed intermediacy prediction method allows a checker's speed improvement. We show the application of our method to two well-Bergercode checker architectural solutions: (1) the threshold function based implementation, and (2) the Berger code partitioning design. We have verified that, as expected, the proposed method can improve the detecting speed of these existing solutions with moderate or minimum increase, and sometimes decrease, in hardware complexity.