Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Self-Testing Embedded Two-Rail Checkers
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Intermediacy Prediction for High Speed Berger Code Checkers
Journal of Electronic Testing: Theory and Applications
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
Embedded Totally Self-Checking Checkers: A Practical Design
IEEE Design & Test
Concurrent Checking of Clock Signal Correctness
IEEE Design & Test
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Compact and Highly Testable Error Indicator for Self-Checking Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Embedded two-rail checkers with on-line testing ability
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
High Speed and Highly Testable Parallel Two-Rail Code Checker
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 1st conference on Computing frontiers
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In this paper, we propose a compact, high-speed, and highly testable parallel two-rail code checker, particularly suitable to implementing embedded checkers. In fact, it requires only two input codewords to satisfy the Totally-Self-Checking or Strongly Code-Disjoint property with respect to a wide set of realistic internal faults. Our checker can be employed to check the correct operation of a connected functional block using the two-rail code, to implement the output two-rail code checker of "normal驴 checkers for unordered codes, or to join together the error messages produced by various checkers (possibly using different codes) present within the same self-checking system. The behavior of our checker has been verified by means of electrical level simulations (performed using HSPICE), considering both nominal values and statistical variations of electrical parameters. We also propose a possible modification to our checker internal structure that makes it able to provide an output error indication remaining latched until the application of a proper reset signal. Depending on the considered application and recovery technique to be employed upon the generation of an error indication at the checker output, one proposed solution or the other may be preferable.