A Totally Self-Checking Error Indicator
IEEE Transactions on Computers
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
A methodology for testability enhancement at layout level
Journal of Electronic Testing: Theory and Applications
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Optimization of error detecting codes for the detection of crosstalk originated errors
Proceedings of the conference on Design, automation and test in Europe
Self-Checking Scheme for Very Fast Clocks' Skew Correction
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
High Speed and Highly Testable Parallel Two-Rail Code Checker
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
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This paper presents a novel concept for concurrently checking the correctness of signals of clock distribution networks of synchronous systems. A VLSI circuitry is then proposed that, based on such a concept, performs the concurrent checking of such signals with respect to permanent and temporary (i.e., transient and intermittent) faults (permanently or temporary) changing their waveforms with respect to those expected in the fault-free case. Such a circuitry is in turn self-checking with respect to its possible permanent, as well as temporary, internal, realistic faults.