Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
Concurrent Checking of Clock Signal Correctness
IEEE Design & Test
Discontinuities Driven by a Billion Connected Machines
IEEE Design & Test
Itanium Processor Microarchitecture
IEEE Micro
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Proceedings of the 1st conference on Computing frontiers
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?
IEEE Transactions on Computers
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Clock Faults Induced Min and Max Delay Violations
Journal of Electronic Testing: Theory and Applications
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Based on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small percentage of such faults result in catastrophic failures easily detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself.