Compiler managed micro-cache bypassing for high performance EPIC processors
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
IEEE Transactions on Computers
SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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The press and the technical community have generated much excitement and speculation about the IA-64 instruction set and the Itanium processor. Intel and Hewlett-Packard have rolled out (one instruction at a time) the instruction set. Intel is rolling out (one transistor at a time) the Itanium processor and other platform components. This special issue provides the broad technical community with a comprehensive introduction to the concepts and mechanisms that form the basis of the IA-64 instruction set and the related Itanium processor products.