Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Test methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC"-III Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Support for Debugging in the Alpha 21364 Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Clock Faults' Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
IEEE Transactions on Computers
Clock Faults Induced Min and Max Delay Violations
Journal of Electronic Testing: Theory and Applications
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In today's high performance (multi-GHz) microprocessors' design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We will show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations' compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in Defect Level. Similarly, we will show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors' design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem will be discussed.