Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing
Journal of Electronic Testing: Theory and Applications
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
Resistance Characterization for Weak Open Defects
IEEE Design & Test
Improving Defect Detection in Static-Voltage Testing
IEEE Design & Test
Probabilistic mixed-model fault diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-oriented testing of mixed-signal ICs: some industrial experience
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Built-in intermediate voltage testing for CMOS circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Correlation between I/sub DDQ/ testing quality and sensor accuracy
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A new quality estimation methodology for mixed-signal and analogue ICs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
FFT-based test of a yield monitor circuit
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
17.2 A Design for Testability Study on a High Performance Automatic Gain Control Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIST Approach for Very Deep Sub-Micron (VDSM) Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPU
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Strategy Sensitivity to Defect Parameters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 1st conference on Computing frontiers
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours
Journal of Electronic Testing: Theory and Applications
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
High Speed and Highly Testable Parallel Two-Rail Code Checker
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modeling Feedback Bridging Faults with Non-Zero Resistance
Journal of Electronic Testing: Theory and Applications
Testing for Resistive Shorts in FPGA Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Self-Checking Voter for High Speed TMR Systems
Journal of Electronic Testing: Theory and Applications
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?
IEEE Transactions on Computers
Test quality analysis and improvement for an embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Using test data to improve IC quality and yield
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Detectability of internal bridging faults in scan chains
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Diagnosis of multiple-voltage design with bridge defect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test escapes: analysis of short defect
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Testing CMOS logic gates for realistic shorts
ITC'94 Proceedings of the 1994 international conference on Test
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Variable supply voltage testing for analogue CMOS and bipolar circuits
ITC'94 Proceedings of the 1994 international conference on Test
Analogue fault simulation based on layout dependent fault models
ITC'94 Proceedings of the 1994 international conference on Test
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