Built-in intermediate voltage testing for CMOS circuits

Authors:
Jing-Jou Tang;Kuen-Jong Lee;Bin-Da Liu
Affiliations:
Deptartment of Electrical Engineering, National Cheng-Kung, University, Tainan, Taiwan 70101, R.O.C.;Deptartment of Electrical Engineering, National Cheng-Kung, University, Tainan, Taiwan 70101, R.O.C.;Deptartment of Electrical Engineering, National Cheng-Kung, University, Tainan, Taiwan 70101, R.O.C.
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract

In this paper, we propose a new testing technique called built-in intermediate voltage testing for CMOS circuits. This technique provides a high quality test which cannot be achieved by conventional functional testing. Three novel circuit designs that can detect faults resulting in intermediate voltage values are presented. These designs can also be used to detect slow transition faults and the metastability of flip-flops. The detection speed, area overhead, circuit complexity, and the performance impact on the circuits under test are analyzed. The results validate the feasibility of these designs in CMOS testing.