Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
CrossCheck: a cell based VLSI testability solution
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Bridge fault simulation strategies for CMOS integrated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Stuck Fault and Current Testing Comparison Using CMOS Chip Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IDDQ Characterization in Submicron CMOS
Proceedings of the IEEE International Test Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
QTAG: A Standard for Test Fixture Based IDDQ/ISSQ Monitors
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
ATS '96 Proceedings of the 5th Asian Test Symposium
Built-in intermediate voltage testing for CMOS circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Realistic Coverages of Voltage and Current Tests
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
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This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.