ATPG based on a novel grid-addressable latch element
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A unified approach for the synthesis of self-testable finite state machines
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A Testable Design of Logic Circuits Under Highly Observable Condition
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Transistor leakage fault location with ZDDQ measurement
ATS '95 Proceedings of the 4th Asian Test Symposium
ADTS: an array defect-tolerance scheme for wafer scale gate arrays
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Modifying User-Defined Logic for Test Access to Embedded Cores
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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A new testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs. The test points are accessed through an on-chip grid of orthogonal probe and sense lines. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. The sizable number of test points improves the testability of the designs by a very large factor. Additionally, analog measurement and signal injection capabilities allow detection of practical CMOS fault modes such as opens, shorts, open or closed FET's and even noise margins.The large observability of CrossCheck based designs reduces the automatic test pattern generation problem to one of providing control only. Several ISCAS benchmark designs are analyzed using CrossCheck cell libraries and fault models. The results show that over 97 percent coverage of a broad range of fault modes, such as opens and shorts, can be obtained on VLSI CMOS designs without the need for large computing resources.