CrossCheck: a cell based VLSI testability solution
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
ATPG based on a novel grid-addressable latch element
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Behavioral synthesis for testability
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Parity-Scan Design to Reduce the Cost of Test Application
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
Design for Testability Using State Distances
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Design-for-testability for synchronous sequential circuits using locally available lines
Proceedings of the conference on Design, automation and test in Europe
On Full Reset as a Design-For-Testability Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
A study on insuring the full reliability of finite state machine
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartII
Multi-frequency, multi-phase scan chain
ITC'94 Proceedings of the 1994 international conference on Test
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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