A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power management techniques for control-flow intensive designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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In this paper, we propose a controllerresynthesis technique to enhance the testability ofregister-transfer level (RTL) controller/data path circuits. Ourtechnique exploits the fact that the control signals in an RTLimplementation are don‘t cares under certain states/conditions. Wemake an effective use of the don‘t care information in thecontroller specification to improve the overall testability (betterfault coverage and shorter test generation time). If the don‘t careinformation in the controller specification leaves little scope forrespecification, we add control vectors to the controller toenhance the testability. Experimental results with examplebenchmarks show an average increase in testability of 9% with a3–4 fold decrease in test generation time for the modifiedimplementation. The area, delay and power overheads incurred fortestability are very low. The average area overhead is 0.4%, andthe average power overhead is 4.6%. There was no delay overheaddue to this technique in most of the cases.