Almost all k-colorable graphs are easy to color
Journal of Algorithms
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Digital signal processing: theory, applications, and hardware
Digital signal processing: theory, applications, and hardware
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Built-In Self-Testing Approach for Minimizing Hardware Overhead
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Detecting undetectable controller faults using power analysis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Controller Testability Analysis and Enhancement Technique
EDTC '97 Proceedings of the 1997 European conference on Design and Test
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controller and the data path parts are individually 100\% testable, the composite circuit may not be easily testable by gate-level sequential ATPG. Analysis shows that a primary problem in test pattern generation of combined controller-data path circuits is the correlation of control signals due to implications imposed by the controller specification. A design-for-testability technique is developed to re-design the controller such that the implications which may produce conflicts during test pattern generation are eliminated. The DFT technique involves adding extra control vectors to the controller. Experimental results show the ability of the controller DFT technique to produce highly testable controller-data path circuits, with nominal hardware overhead.